Introduction

Online-VAMS is a free Verilog-AMS simulator. Verilog and Verilog-AMS files may be uploaded, with simulation waveforms available for download at the end of simulation, and viewable with any third-party waveform viewer. In addition, example designs may be selected, with some larger SMPS designs available to demonstrate online-VAMS's high speed (eg 12-phase PCMC SMPS in PWM mode simulating at 2ms/min).

At the architectural level, online-VAMS is implemented using Presilic's neoVAMS compiler and mixed-signal simulation engine VPI plugin, coupled with Icarus Verilog 12.0. Further information on neoVAMS, and how to use it with your favorite SystemVerilog simulator, is available in section neoVAMS and at www.presilic.com. Further information on Icarus Verilog is available at the Icarus website.

Online-VAMS is intended primarily as an educational resource. No size constraints are imposed on the designs, however daily simulation quotas are applied as per this site's Conditions Of Use.

Features

With online-VAMS, you can:

  • upload, compile and simulate Verilog/Verilog-AMS code
  • download the results and view the waveforms with any VCD waveform viewer
  • run examples, including large modules, eg 12-phase SMPS, some using advanced neoVAMS features such as circuit partitioning and solution acceleration
  • for custom code, adjust simulation parameters eg minimum and maximum time steps

Getting Started

Pre-requisites

  • install your favourite text editor in order to create/modify an AMS design.
  • install a VCD waveform viewer. GTKWave is free and works well.

Simulating a Custom Design

  • create a design consisting of Verilog-AMS files (.vams) and Verilog files (.sv or .v). Browsers do not support selection of files from multiple directories, so all files must reside in a single directory. NOTE: do not include $dumpvars() and $dumpfile() tasks as online-VAMS already dumps all available signals.
  • under the 'Design' menu:"
    • select 'Design Type': custom
    • click on 'Design Files' and select all the files needed in the design.
      • this step is required only once for a given set of files - any subsequent modifications applied to the content of those files are automatically applied to future simulation runs.
    • in 'Top Module' enter the top module of the design.
  • press 'RUN' at the bottom of the output/terminal window, or 'run' under the 'Sim Controls' menu.

Viewing the Results

  • download the VCD file: press 'vcd download' under the 'Sim Controls' menu.
  • open the VCD file using your viewer. All nets and variables in the design will have been saved during simulation. Note that the potential on analog nets must be probed and converted to real values during simulation as described below.
  • note: results are retained on the server only for a few hours.

Probing Analog Nets

Commercial simulators store the potential of analog nets in propriatory format. To view analog net potential from online-VAMS simulations, the potential must be probed/sampled and stored in real variables. To do this, either:

  • instantiate a FMS_Vin component - the probed voltage is available as ".V". See one of the simple examples.
    • eg FMS_Vin Vprobe_net01(net01);
      • the probed/sampled potential of 'net01' is then available as "Vprobe_net01.V".
  • or:
  • probe/sample the net's potential using the AMS function absdelta().

Modify and Re-run

Modify or add to the design as required, re-run, and review the results. There is no need to re-select the design files if only file content has been modified.

Simulation Options

A small set of simulation options/parameters (more to come) may be set when simulating custom designs:

  • under the 'SimOptions' menu:"
    • for most fields, simply enter a meaningful value. Fields are currently not validated in the browser.
    • when defining macros (`defines), these are specified in a simulator-agnostic way (not Icarus command line format):
      • macro1=value1, macro2=value2, macro3
  • simulation options are not available when simulating from the set of examples.

Simulating an Example Design

A range of example designs are available for simulation. The simpler examples can be used as a way of getting started - design files are generally available for download. Large complex SMPS design examples are provided primarily to demonstrate the speed of neoVAMS. Design files may be available for download for portions of the large examples/demos (a complete set requires an NDA).

To simulate an example design:

  • under the 'Design' menu:"
    • select 'Design Type': examples
    • click on 'Example' and select from the list of examples.
    • simulation options will not be available for examples.
  • press 'RUN' at the bottom of the window, or 'run' under the 'Sim Controls' menu.
  • for larger designs, simulation statistics (eg number of steps, CPU time) can be viewed by selecting the 'Info' tab (adjacent to the 'Output' tab)
  • view simulation results as per custom designs.
  • to download the design files (if available), press 'src download' under the 'Sim Controls' menu.

Simulator Issues/Limitations

The sections below list some of the functional and/or language limitations of Icarus Verilog and neoVAMS.

Icarus Simulator Issues/Limitations

  • doesn't finish in some cases

Icarus Language Limitations

Icarus is a Verilog simulator, with very few SystemVerilog language extensions. Lack of SystemVerilog support should not be a barrier for the intended use of online-VAMS, however if you need SystemVerilog or UVM, consider using an offline solution using licensed neoVAMS with your favorite SystemVerilog simulator.

Some additional limitations are associated with Icarus's VPI implementation - in such cases a purely discrete design will work correctly but 'online-VAMS' will not.

  • VPI issue with multiple levels of hierarchy with the same hierarchy name (eg "top.i1.i1")
  • VPI issue with real arrays
  • VPI issue with net bit selects, eg top.stim[0] - avoid continuous domain vector nets
  • no support for real parameter arrays

neoVAMS Language Limitations

Some language limitations currently exist in the following areas:

  • analysis functions: support only for DC and TRANSIENT
  • generate constructs: limited support
  • case constructs: not supported in analog context
  • vector branches: limited support
  • user defined analog functions: currently no hierarchical calls and no access to module parameters
  • analog operators and analog event control statements: all but a few implemented
  • parameter ranges: parsed but ignored
  • SPICE compatibility (ability to load Spice netlists): future...

neoVAMS

neoVAMS is an extension for standard Verilog and SystemVerilog simulators, adding seamless Verilog-AMS simulation capability.

Aimed at accelerating functional verification of very large mixed signal modules and SoCs requiring transient behavior, it incorporates several innovative features while requiring near zero changes to existing tool flows.

Some of the design examples included with online-VAMS aim to demonstrate the high speed, including a 12-phase PCMC SMPS design running in PWM mode at 2ms/minute.

neoVAMS features:

  • Verilog-AMS VPI plug-in for Verilog/SystemVerilog simulators
  • fast multi-instance analog solver supporting circuit partitioning
  • solver acceleration (up to 2x) for circuits exhibiting a reasonalble level of repetition (eg SMPS)
  • support for auto-inserted supply-sensitive Connect Modules when used with Cadence® Xcelium/Spectre
  • includes FMS-DE: single and multi-channel Discrete Electrical (DE) networks supporting voltage and current resolution; a 'plain wire' alternative to SystemVerilog UDNs
  • real-time GUI-based profiler for identifying and fixing simulation-speed bottlenecks
  • compatible with Cadence® Xcelium, Modelsim/Questa-Intel® FPGA, Icarus Verilog; untested with Synopsys® VCS

Further information is available at www.presilic.com.

Conditions Of Use

All users of "online-VAMS" and/or this site must agree to the conditions, policies, and constraints laid out in the sections below:

Permitted Use

  1. "online-VAMS" may be used, free of change, for personal, educational, or commercial use.

Liability

  1. Presilic accepts no liability or claim against it for the use of this site. Users accept sole liability and use "online-VAMS" at their own risk.
  2. Presilic accepts no responsibility for unauthorized access to design files and/or other user data uploaded to this site.
  3. Presilic does not guarantee the availability of this website, or availabity of support.

Privacy Policy

  1. Design files and simulation data are not shared with any person or entity.
  2. Design files and simulation data are retained on the server for a short period of time (a few hours) after which they are deleted.
  3. Usage data is not shared with any person or entity.
  4. No personal information is requested, collected or shared.
  5. Cookies are used only for correct functionality, and are not shared.
  6. Resource usage information collected over short periods of time, for the purpose of resource limiting and fair use, is not shared with any person or entity.

Fair Use Policy

  1. Usage information is used by the server to limit resource usage and ensure fair use. Such information may include, per IP, session and job CPU usage, number of runs, number of active sessions.
  2. Control of resources may result in killing of jobs, placing limits on the number of users (per IP), and/or prevent further simulations until quotas are refreshed.
  3. Presilic reserves the right to block unfair usage, without notice.

Support

For technical support of "online-VAMS", please first refer to the help available on this page. If the information is not available on this help page, please contact us, providing as much detail as possible. Suggestions are also welcome.

For technical support of Icarus Verilog", please navigate to the Icarus website to view the documentation. To report an issue (with Icarus), or view current issues, please follow the documented process.

Updates

ver 2025.11.0

  • Language: support for analog operators and event control statements within analog for loops
  • FIX: various minor issues
  • Examples: added adc-dac
  • Help Page: updates

ver 2025.10.0

  • Language: added support for user defined analog functions

ver 2025.09.0

  • Language: added support for 'signed' keyword in port/net/reg declarations
  • Language: added support for discipline specification as part of port declaration
  • Language: added 'timer' analog event function, and support for analog event statements
  • FIX: '\logic' discipline not applied correctly
  • online-VAMS: fixed rare lock-up of job scheduler preventing users from running online sims

ver 2025.06.0

  • for/while/repeat loop support added; [note: analog_for loop support still very limited: contribution statements are supported, but filters are not (yet)]
  • FIX: various minor fixes

ver 2025.02.0

  • access functions associated with 'electrical' discipline no longer hardwired
  • FIX: 'constants.vams' was missing
  • FIX: multiple issues associated with assignment to discrete variables and ports from within an analog block

ver 2024.10.0

  • initial release of online-VAMS