Introduction

Pre-silicon functional verification of large System-on-Chip (SoC) designs can be quite challenging. High functional coverage depends on a systematic and hierarchical approach where extensive functional verification is carried out at both the module-level and at SoC-level.

Functional verification at module-level generally requires reasonably accurate transient behaviour, necessitating the use of Spice, and for large complex modules a combination of Spice and AMS, or purely AMS models. Even with the use of models, relatively slow simulation times may limit functional coverage at this level.

For functional verification at SoC-level, Real Valued modeling (RVM) combined with analog wires (eg FMS-DE) is fast and highly effective in the detection of connectivity errors, configuration errors, and unexpected inter-module behavioral dependencies. Detailed Spice/AMS models cannot be used at SoC level, at least not for complex modules, due to unacceptably slow simulation times.

The use of two sets of models, RVM at SoC-level, and Spice/AMS at module level, is obviously not ideal. It results in significant additional development and maintenance costs, as well as the need for different skill sets, and usually a longer verification period and delayed tape-out. Furthermore, slow models / simulation at module level may result in lower than desired functional coverage.

The goal of FMS-MS is to enable one set of detailed module-level models to be easily re-used at SoC level with acceptable simulation times, thus removing the need for two sets of models and the associated cost. Faster models also allow increased module-level functional coverage.

Overview of FMS-MS

FMS-MS provides a set of familiar Spice-like analog components (including behavioral sources), AMS-like functions/filters (eg ‘cross’, ‘transition’), and Discrete Electrical (DE) analog wires and components, to enable the creation of fast efficient detailed behavioral models at module-level and below. FMS-MS also provides a unique partitioned circuit mixed signal solver to solve the resulting system of models.

The unique mixed signal solver achieves high simulation speed primarily using the following mechanisms:

instead of solving the analog portion of an SoC as one single circuit, the SoC is partitioned into smaller largely independent circuits which are solved separately as part of a loosely coupled system
algorithms exploiting repetition in circuits (Switch Mode Power Supply (SMPS) instances are a good example)

FMS-MS components/functions/filters are provided in the form of SystemVerilog modules. The mixed signal solver and other functionality is provided in the form of a VPI shared library which is compatible with a number of SystemVerilog digital simulators.

Circuit Independence and Partitioning

It is easy to understand why partitioning is effective if we recognise the relative independence of module instances within an SoC, and their differing requirements in terms of solutions per unit time based on their differing stimulus and different components. When instances are largely independent, then re-solving the entire system each time one instance needs re-solving is clearly inefficient.

Consider an SoC comprising two SMPS instances with separate loads; one SMPS is enabled, and the other not. Clearly the instance which is disabled requires fewer (or near zero) solutions per unit time compared to the instance which is enabled. This relative independence may be far more fine grained: for example, when one instance is in PWM mode and the other is in PFM mode with only one phase active.

In practice, this approach involves the partitioning of a large circuit into largely independent smaller circuits, which are then solved independently, usually with a significant increase in system simulation speed. Clearly partitioning is meaningful only if the resulting partitioned system, from a functional verification perspective, behaves as if it were not partitioned. Partitioning is achieved by introducing Partition Interface Elements between analog circuits, so partitioning does not mean complete isolation, and the degree to which analog circuits are coupled is controlled by setting the A2D conversion sensitivity of each connection appropriately. In the majority of cases, SoCs can be partitioned at module instance boundaries, although partitioning can be applicable and useful at much lower levels, especially within large complex modules.

SMPS SoC Use Case

As a practical example consider an SoC comprising four quad-phase 13MHz PCM SMPS instances sharing a common ground and 3.7V resistive supply, with 0.98V outputs connected to separate loads. Power Management IC (PMIC) SoCs comprising many bucks and LDO regulators are common, and high speed multi-phase SMPS instances typically simulate slowly even at module level, so this use case should be considered realistic, although some SoCs may be considerably larger.

The quad-phase SMPS design modelled here is quite basic, with minimal digital control logic, but does feature PWM and PFM mode, soft start, and zero crossing detect. The phase clocks are 3.25MHz, offset equally relative to one another. The output voltage and inductor current are available to the test-bench with configured A2D resolution / sensitivity of 2mV, and 10mA respectively (nominal phase current for most PWM tests is ~4A). These resolutions are considered sufficient in this case, however can be increased as required. Note that higher resolutions may increase simulation time. A2D time tolerance is set to 40ns.

Performance Gains due to Partitioning

Table 1 clearly shows the positive impact on simulation performance for a variety of tests, due to partitioning a single SoC into four separate SMPS instances. Each test involved a 0.25ms soft start followed by 0.75ms in PWM mode. The common 3.7V supply (with 10mΩ resistance) was connected to each instance via a D2A Partition Interface Element, which passes the supply voltage downstream, but averages downstream current before drawing it from the upstream supply. This results in loose coupling of the four instances – each instance current may effect the common supply voltage which in turn may affect each instance, but the coupling is reduced by averaging the current. From a functional verification perspective, this should provide very similar system-level behavior to that of an unpartitioned SoC.

DUT mode	Partitions
DUT mode	1	4
4 bucks enabled, 4 active phases / buck	1.0	0.36
4 bucks enabled, 1 active phase / buck	0.3	0.1
1 buck enabled, 4 active phases / buck	0.82	0.086

Table 1: Relative simulation time, contiguous vs partitioned, various test configurations

Acceleration of Circuits with Repetition

The FMS-MS mixed signal solver implements an algorithm effective in speeding simulations containing circuits exhibiting a reasonable level of repetition. The level of performance gain depends on circuit and test (stimulus), with an acceleration of 2x typically observed with the SoC test case comprising four quad phase SMPS instances described earlier. Table 2 illustrates the performance gain observed in a variety of tests / configurations, for unpartitioned and partitioned alike.

Test	Enabled instances	Active phases	Partitions	Perf gain
1ms PWM (0.25ms soft start)	4	4	1	1.92
	4	1	1	1.68
	1	4	1	3.04
	4	4	4	2.0
	4	1	4	1.98
	1	4	4	2.14
50ms PFM (0.25ms PWM soft start)	4	4	4	1.72

Table 2: Performance gain using acceleration for circuits with repetition

Actual Simulation Times

The range of actual simulation speeds for the partitioned SMPS SoC use case, presented in terms of ms/minute, is shown in Table 3. The compute environment used was Linux running on a quad-core 3.3 GHz i5 CPU. Times vary a little across different simulators, however in most cases the analog contributes to 75-85% of simulation time, so the results will be representative of most current discrete simulators. Speeds are for single thread (single core).

Test	Enabled instances	Active phases	Speed ms/min
1ms PWM (0.25ms soft start)	4	4	1.5
1ms PWM (0.25ms soft start)	1	4	5.5
50ms PFM (0.25ms PWM soft start)	4	4	110
50ms PFM (0.25ms PWM soft start)	4	1	250

Table 3: Simulation speeds for a variety of tests / configurations

Table 3 suggests that although some tests/ configurations are still rather slow, very good speeds can be achieved if most instances are not configured to be fully loaded in PWM mode. NOTE: actual times will vary with SMPS / test-bench design!

Other Significant Performance Impacts

A2D Sensitivity control:

controlling the sensitivity of

A2D, for discrete(real) outputs used by other models or by the test-bench, can significantly impact on speed, as additional time points (solutions) may be required in order to meet the A2D requirements. Controlling A2D sensitivity also controls the degree of coupling between models. Easy to use controls are built into all components which monitor voltage or current, including DE components. Controls include absolute and relative delta, and for some, individual time tolerance.

SoC Configuration and Test Scenarios:

in the

results presented so far on relative and absolute performance, it is clear that simulation times are highly dependent on the overall SoC configuration and scenario being tested. Some scenarios will run too slowly to be practical. On the flip side, if functional testing focuses on a few instances at a time (which is how tests are usually written), with other instances remaining either disabled or in a mode where they contribute relatively little to overall run time, then simulation performance can be exceptional. For example, it is unlikely that in every PMIC test, all SMPS regulators need to be fully loaded or even enabled – most could remain disabled or in PFM mode.

Lean Models:

bearing in mind that the purpose of the

models is to support (detailed) functional verification and not circuit characterisation, models must use the simplest/ fastest components and equations suited to the task. This means for example using a resistor and PWL diode in place of a MOS device to model the switch in a regulator’s power stage. This is consistent with the general modeling principles of abstraction and simplification.

Co-simulation with Spice/Verilog-AMS

Two important use cases for co-simulation typically arise when developing or using RVM or FMS-MS models for large / complex SoCs.

Model Development and Calibration:

very often

functional specifications are not available for analog / mixed-signal circuits, at least not early enough. Functional models are often developed based on the currently available version of the Spice-level schematic. Co-simulation assists at this point by allowing simple discrete stimulus and monitoring to be used to observe operation of the netlisted schematic, and later the side-by-side calibration of discrete / FMS-MS model and schematic. If automated checking is added, calibrations can be regularly regressed to ensure model and schematic continue to match.

Mixed Spice+Model Simulation Test Environment:

cases arise where it’s either not feasible

(or not desirable) to simulate a particular module using an RVM or FMS-DE model, instead using Spice/AMS. Alternatively, selected models may be used in a primarily schematic-based environment to partially speed simulation. In either case the test environment comprises both Spice and models. In other cases a complex module may comprise many individual submodules which are modelled separately and brought up / integrated individually or in groups. This may be especially true where a particular circuit requires complicated stimulus not easily replicated in a calibration environment.

All use cases described above represent instances where the blocks being mixed are functionally largely independent, independently solvable, and correspondingly the connections between blocks can essentially exist as ideal or resistive voltage or current source-sink pairs.

FMS-MS provides single channel Interface Elements for integration with Verilog-AMS. These Interface Elements dynamically support ideal and resistive networks, and their A2D sensitivity can be set by DE network components, in

order to optimise the number of conversions, especially in cases where analog noise is present.

SystemVerilog UDN Option

An optional FMS-MS implementation is also available where network connectivity is established using SystemVerilog User Defined Nets, rather than VPI. A comparison of VPI and SV UDN implementations is shown in Table 4.

Feature / Limitation	VPI	SV UDNs
Analog elaboration with HUGE designs	potentially slower	potentially faster
Channel potential viewable on net segments in waveform viewer	✗	✓
Connectivity through protected envelopes	✗	✓
Simulator additional license feature	✗	✓
Coexistence with 4-state	✓	✗
Multiple network types / UDNs on the same net	✓	✗
Need to parameterise multi-channel switch based on type	✗	✓
Co-simulation with AMS	✓	✓

Table 4: comparison of VPI and UDN connectivity implementations

Key Features

fast multi-instance analog solver supporting analog circuit partitioning
solver optimisation (up to 2x) for circuits exhibiting a reasonable level of repetition (eg SMPS)
includes FMS-DE: single and multi-channel Discrete Electrical (DE) networks supporting voltage and current resolution, for RVM subcircuits.
tight / automatic integration of DE networks/circuits with analog (MS) circuits
variable value Spice-like components with integrated voltage/ current monitoring
high level AMS-like functions/filters such as ‘transition’ and ‘cross’
A2D controls on a per net basis, to easily control the degree of circuit coupling
connect modules for AMS / Spice co-simulation
circuit topology checking

SystemVerilog UDN connectivity option
project/file based configuration of features, and transient error message controls
a real-time profiling tool to help improve simulation speed, showing simulation speed, relative CPU load of each partitioned circuit, and limiting factors for each partition such as inputs with the highest transition rate, and components limiting the step size due to error tolerance or A2D constraints.

Ongoing Development

FMS-MS is under continuous development and improvement. Features planned for the near future include:

additional functions/filters, such as ddt, slew, and Laplace

Ongoing research and development will continue in the area of simulation performance, and also in tool-assisted /semi-automated circuit partitioning.

Availability

FMS-MS is licensed software, provided as SystemVerilog modules and VPI libraries, available on Linux for the following simulators:

Cadence^® Xcelium
Mentor^® Modelsim / Questasim

Product Support

Presilic provides email support as standard, as well as dedicated maintenance contracts where required. Presilic has a great deal of experience with both RVM and Verilog-AMS model development, and can guide and assist where required.

Verilog-AMS Solution

Presilic also offers a fast multi-partition Verilog-AMS simulator plug-in, called FastAMS. Refer to seperate documentation for details.